Prof Simon Moore

Name:	Prof Simon Moore
Affiliation:	University of Cambridge
E-mail:	(only provided to users who are logged into talks.cam)
Last login:	Wed Nov 13 17:46:55 +0000 2024

Public lists managed by Prof Simon Moore

• Computer Laboratory Computer Architecture Group Meeting

Talks given by Prof Simon Moore

Obviously this only lists talks that are listed through talks.cam. Furthermore, this facility only works if the speaker's e-mail was specified in a talk. Most talks have not done this.

• CHERI: a step change in security at the hardware/software interface
• Tutorial on Data Driven Computation
• Design for device variability in nano CMOS

Talks organised by Prof Simon Moore

This list is based on what was entered into the 'organiser' field in a talk. It may not mean that Prof Simon Moore actually organised the talk, they may have been responsible only for entering the talk into the talks.cam system.

• Automated Reasoning at AWS, and Applications in Cryptography
• Modern Cache Prefetching and Page Size Aware Cache Prefetching
• Wally: Bridging he CPU Education-Implementation Gap
• Rivos Founder's Talk: Why RIsc-V? Why Open Source? Why is Architecture back?
• Fast and Efficient Deployment of Security Defenses via Microcode Customization
• Making Python Fast: Using Hardware-Software Co-design to Address Inefficiencies in Dynamic Language Runtimes
• Directed Speculation in Multi-core Memory Systems to Improve Performance and Efficiency
• Intra-Core Loop-Task Accelerators for Task-Based Parallel Programs
• Energy-Quality Scalable Adaptive VLSI Circuits and Systems – The Way towards the Next 10X Energy Reduction
• FPGA Implementations of High-bandwidth and Low-Latency Machine Learning based on Online Kernel Methods
• Design for Security Test against Fault Injection Attack, and Fast Test with Compressive Sensing
• Barrier-Aware Warp Scheduling for Throughput Processors
• The CAVA Computer: Exceptional Parallelism and Energy Efficiency
• Neural simulation on diverse computational hardware
• USB Type-C: How hard is it to pick two resistors?
• Randomised testing of a microprocessor model using SMT-solver state generation
• Virtual Prototyping, Virtual Platforms, and System Simulation for Embedded System and Software Development
• Energy Efficient Computing System - Research in NICS CAD Tsinghua
• Adaptive Resolution of Information Flow Constraints
• Exposing Fine-grain Concurrency in Sequential code with a Dataflow Compiler IR
• Architecture Support for Accelerator-Center Architectures
• HDL Code Generation from MATLAB and Simulink
• System-Level Management of Hybrid Accelerators
• Constructive Approach to Computer Architecture
• ON-CHIP DEBUG SUPPORT TO ADDRESS COMPLEXITY IN MULTIPE PROCESSOR SYSTEMS-ON-CHIP
• Device Mechanism: Rethinking Driver Development
• Communication Challenges for Extreme-Scale, Real-Time Neural Network Simulation
• Software lock elision for x86 machine code
• Introducing the Computer Architecture Group
• Experiences Creating Chromebook
• Threads, caches and networks in CMP systems
• Verification of Microarchitectural Refinements in Rule-based Systems
• Hardware Protection for Trusted Software
• Implementation of ISE for the micro-threaded model in LEON3 SPARC
• The Foundations of Apple-CORE:- DRISC, Microthreading and SVP
• Using Processor Hardware Counters in Picking the Optimal Work-Stealing Policy
• Field programmable parallel computing in signal and image processing - is application development too hard and what can be done about it?
• Steps Towards a Flexible Manycore Fabric
• Short-Read DNA Sequence Alignment with Custom Designed FPGA-based Hardware
• Low Power Photonic Networks for Shared Memory Computers
• Time-Driven Switching: Principles and Implementation
• Predictive Models for Microarchitectural Adaptation
• Building an 18 core ARM chip multiprocessor for neuronal simulation
• The RLOC is Dead -- Long Live the RLOC
• Welcome meeting
• Enabling Runtime Monitoring on Multicores for Performance and Reliability
• Accelerator: A data-parallel DSL for programming heterogonous systems
• Massively Parallel Processor Array: an FPGA Replacement?
• Computer System Emulation using Multiple FPGAs
• Proximity Coherence for Chip Multiprocessors: A communication-centric cache coherency protocol extension
• PWRficient Techniques for Today & Questions for Tomorrow
• A Photonic Chip-to-chip Network for C3D
• A Communication Characterization of Splash-2 and Parsec
• Flow-Aware Allocation for On-Chip Networks
• Parallel External Memory Model for Multicore Architectures
• FPGA's NoC Freedom: You bought it, so why not use it
• Optical Interconnect - Tutorial and Initial Thoughts
• Hardware multithreading
• BEE3: Revitalizing Computer Architecture Research
• Combining Scratch-Pad Placement with Loop Parallelisation for FPGAs
• Map-reduce as a Programming Model for Custom Computing Machines
• Xilinx ChipScope Tutorial
• The next resource war: computation vs. communication
• Synchronisation Mechanisms - A Tutorial
• Tutorial on Data Driven Computation
• System Modeling and Dynamic Reconfiguration in Xilinx Research
• High-Performance Processing with Field-Programmable Logic
• Hardware defences against side channel and invasive attacks
• Programmable Logic Core Based Post-Silicon Debug For SoCs
• Reading group: Revisiting the Sequential Programming Model for the Multicore Era
• Designing Circuits with Parallel Programs
• All day seminar: Parallel Computing Everywhere
• IET/BCS talk: The Internet - Where it came from & where it is going
• Design for device variability in nano CMOS
• Communicating Process Architecture for Multicores