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University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > Intra-Core Loop-Task Accelerators for Task-Based Parallel Programs
Intra-Core Loop-Task Accelerators for Task-Based Parallel ProgramsAdd to your list(s) Download to your calendar using vCal
If you have a question about this talk, please contact Prof Simon Moore. Note unusual time Task-based parallel programming frameworks offer compelling productivity and performance benefits for modern chip multi-processors (CMPs). At the same time, CMPs also provide packed-SIMD units to exploit fine-grain data parallelism. Two fundamental challenges make using packed-SIMD units with task-parallel programs particularly difficult: (1) the intra-core parallel abstraction gap; and (2) inefficient execution of irregular tasks. To address these challenges, we propose augmenting CMPs with intra-core loop-task accelerators (LTAs). We introduce a lightweight hint in the instruction set to elegantly encode loop-task execution and an LTA microarchitectural template that can be configured at design time for different amounts of spatial/temporal decoupling to efficiently execute both regular and irregular loop tasks. Compared to an in-order CMP baseline, CMP +LTA results in an average speedup of 4.2x (1.8x area normalized) and similar energy efficiency. Compared to an out-of-order CMP baseline, CMP +LTA results in an average speedup of 2.3x (1.5x area normalized) and also improves energy efficiency by 3.2x. Our work suggests augmenting CMPs with lightweight LTAs can improve performance and efficiency on both regular and irregular loop-task parallel programs with minimal software changes. Bio: Christopher Batten is an Associate Professor in the School of Electrical and Computer Engineering at Cornell University, where he leads a research group focusing on energy-efficient parallel computer architecture for both high-performance and embedded applications. His work has been recognized with several awards including a Cornell Engineering Research Excellence Award (2015), an AFOSR Young Investigator Program award (2015), an Intel Early Career Faculty Honor Program award (2013), an NSF CAREER award (2012), a DARPA Young Faculty Award (2012), and an IEEE Micro Top Picks selection (2004). His teaching has been recognized with the Ruth and Joel Spira Award for Excellence in Teaching (2016) and two Michael Tien ‘72 Excellence in Teaching Awards (2013,2017). Prior to his appointment at Cornell, Batten received his Ph.D. in electrical engineering and computer science from the Massachusetts Institute of Technology in 2010. He received an M.Phil. in engineering as a Churchill Scholar at the University of Cambridge in 2000, and received a B.S. in electrical engineering as a Jefferson Scholar at the University of Virginia in 1999. This talk is part of the Computer Laboratory Computer Architecture Group Meeting series. This talk is included in these lists:
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