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The Foundations of Apple-CORE:- DRISC, Microthreading and SVP

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This presentation will introduce the main abstractions adopted in the Apple-CORE project for the design of general-purpose multi-core processors. The strategy adopted was to capture, in the ISA , all of the concurrency exposed in an application. Then when matching this to available resources, to auto-sequentialise the code so as to avoid the potentials pitfalls to concurrent execution, such as resource deadlock. This is in contrast to the current approach of auto-parallelising sequential code (out-of-order processors) or capturing concurrency according to the concurrency requirements of a given target (GP multi-cores, GP GP Us etc.).

Chris Jesshope holds the chair of System Architecture Engineering at the University of Amsterdam and leads the Computer Systems Architecture group in the Institute for Informatics. He has been involved in all aspects of parallel computers over his 35-year research career, from programming early supercomputers such as the Illiac V and Cray 1, through to designing silicon circuits for the implementation of parallel computers. The CSA group has developed core compilers, operating systems and software emulation for the Apple-CORE general-purpose multi-core.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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