University of Cambridge > > Computer Laboratory Computer Architecture Group Meeting > FPGA's NoC Freedom: You bought it, so why not use it

FPGA's NoC Freedom: You bought it, so why not use it

Add to your list(s) Download to your calendar using vCal

If you have a question about this talk, please contact Prof Simon Moore.

Note unusual time and day

As high performance systems scale to 10s and 100s of nodes on a single die, Network-on-Chip (NoC) implementations allow more effective scaling of performance. Initially, NoCs topologies were only used for designs in ASIC technology. Now the largest commercial FPG As can also implement systems with more than 100 processing nodes, making NoC topologies an essential consideration for high performance designs. However, FPG As and ASI Cs are different technologies. ASI Cs are customized to an application, including only those resources that are actually required for the system. FPG As, on the other hand have fixed resources available that exist independent of their usage in the final design. This talk will present results from our current work to quantify how the fixed routing resources of an FPGA affects the freedom of a designer to create an application-specific topology for their system that may improve performance over traditional topologies. The results presented here will include effects on routability and performance from variables such as: - the number and size of nodes in the system - the node degree - the communication link size - the device architecture - and homogeneous versus heterogeneous network nodes

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

Tell a friend about this talk:

This talk is included in these lists:

Note that ex-directory lists are not shown.


© 2006-2024, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity