Combining Scratch-Pad Placement with Loop Parallelisation for FPGAs

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• George Constantinides
• Wednesday 11 June 2008, 16:15-17:15
• SS03, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Prof Simon Moore.

I will discuss some joint work with my PhD student, Qiang Liu, on how to combine loop parallelisation with custom memory subsystem design, targeting FPGA -based computation. We will show that the dependence between the two problems can be exposed and optimized over using a form of constrained optimization called “Geometric Programming”. I will try to find time to begin the talk with an overview of convex optimization techniques in general, and geometric programming in particular, in the hope that some of you may find an application for similar techniques in your own work.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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