Field programmable parallel computing in signal and image processing - is application development too hard and what can be done about it?

Add to your list(s) Download to your calendar using vCal

• David Kearney, University of South Australia
• Thursday 21 April 2011, 14:15-15:15
• Lecture Theatre 2, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Prof Simon Moore.

Note unusual time

FPG As once had a unique position in computing because they could be massively parallel on a single chip. This unique parallel identity is fading thanks to competition from GPUs and multi-core. The FPGA ’s uniqueness now relies more on its customisable architecture, direct high speed I/O and perhaps lower power. Some argue that the extra development effort required for custom architecture FPGA applications is too high to compete in this new environment. They predict the demise of FPG As in all but a narrow niche unless something is done about the development process (Some advocate an open source FPGA as a motivator for faster adoption of new tools).On the other hand those in the fixed architecture community are facing a similar crisis as the reality of parallel application development emerges. This presentation describes research results that explore issues in this controversy. The topics covered include:

1. rule based abstractions for hiding the complexity in synchronization in concurrent applications,
2. the primacy of spatial abstractions in future parallel computing,
3. proposals to standardize application development on FPG As for signal processing and image processing
4. a partial answer to the question: “What should a “compiler” for FPGA based applications do?” and
5. the relationship between hardware and software research in parallel computing for FPG As and the search for better abstractions

About the presenter

David is Associate Professor of Computer Science at the University of South Australia in Adelaide. He has published 108 refereed journal and conference papers, been awarded more than $A1 million in competitive grants and has supervised to graduation 12 higher degree by research students. He has previously worked on asynchronous architectures but in the last 15 years has concentrated in the area of reconfigurable computing with FPG As. He is especially interested in languages and operating systems for reconfigurable computing in the domain of image and signal processing.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

This talk is included in these lists:

• All Talks (aka the CURE list)
• Cambridge talks
• Computer Laboratory Computer Architecture Group Meeting
• Department of Computer Science and Technology talks and seminars
• Interested Talks
• Lecture Theatre 2, Computer Laboratory, William Gates Building
• School of Technology
• Trust & Technology Initiative - interesting events
• bld31

Note that ex-directory lists are not shown.