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Implementation of ISE for the micro-threaded model in LEON3 SPARC

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The talk will describe instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPAR Cv8 processor. An architecture of the developed processor will be presented and its key blocks described – cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro and Virtex5 FPG As. The extensions will be evaluated in terms of extra resources needed, and the overall performance of the developed processor will be shown for a simple DSP computation typical for embedded systems.

Bio: Martin Danek received his PhD from the Czech Technical University in Prague in 2004, where he researched physical design algorithms for FPG As. During his PhD he spent one year at the ICSC , UWE Bristol studying emergent behaviours in distributed multi-agent systems. After joining UTIA in 2003 he focused on tools and methods for using of partial runtime reconfiguration in FPG As. Recently he has become interested in efficient architectures with pipelined functional units and their implementations in FPG As, and in methods that increase the level of abstraction in digital design.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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