RISC Instructions for Capability Acceleration

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• Jonathan Woodruff
• Friday 10 June 2011, 16:00-17:00
• SC04, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Robert Mullins.

The CTSRD project at the Cambridge Computer Laboratory is developing a MIPS processor with custom security extensions to accelerate capability systems. Capability hardware systems allow the enforcement of the principle of least privilege in the lowest levels of computation. In the 1960s and 70s there was much exploration in this space but the market did not demand such stringent security. Security issues are now much more threatening in the market and we are building an extended MIPS processor to enable fast capability-based systems which is also able to run legacy software natively. I will describe the processor architecture designed so far and software use models planned by our systems team.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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