University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > RISC Instructions for Capability Acceleration

  Browse A-Z

Log in

University Account External (via Google)

🔐 Log In

Information on

Subscribing to talksdetails Finding a talkdetails Adding a talkdetails Disseminating talksdetails Help and Documentationdetails

ℹī¸ Information

RISC Instructions for Capability Acceleration

Download to your calendar using vCal

If you have a question about this talk, please contact Robert Mullins .

The CTSRD project at the Cambridge Computer Laboratory is developing a MIPS processor with custom security extensions to accelerate capability systems. Capability hardware systems allow the enforcement of the principle of least privilege in the lowest levels of computation. In the 1960s and 70s there was much exploration in this space but the market did not demand such stringent security. Security issues are now much more threatening in the market and we are building an extended MIPS processor to enable fast capability-based systems which is also able to run legacy software natively. I will describe the processor architecture designed so far and software use models planned by our systems team.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

This talk is included in these lists:

Note that ex-directory lists are not shown.

Other lists

CU Israel Society THE THERAPETIC EFFECTS OF QUALITY MUSIC The Senior Parlour, Gonville & Caius College, Cambridge

Other talks

Title to be confirmed Afternoon Break The spread of environmental cost-benefit analysis in UK government, c.1966-1995: representing the public in the Anthropocene Online Causal Inference Seminar Max Perutz Lecture - Title TBC Decoding genomic chaos - a pancancer compendium of chromosomal instability
 

Š 2006-2025 Talks.cam, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity