CHERI - Architectural support for software memory protection and compartmentalisation

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• Robert N. M. Watson - University of Cambridge, Computer Laboratory
• Wednesday 22 February 2017, 16:15-17:15
• Lecture Theatre 1, Computer Laboratory.

If you have a question about this talk, please contact David Greaves.

Capability Hardware Enhanced RISC Instructions (CHERI) extend a conventional RISC architecture with support for “capabilities” — pointers whose integrity is protected by the hardware, extended with protection metadata such as bounds and permissions, and constrained by security properties such as monotonicity. This low-level primitive is a foundation on which a broad range of software protection properties can be built and incrementally deployed: fine-grained, referential memory protection for C/C++-language programs; protections against control-flow attacks such as ROP and JOP ; granular and efficient in-address-space isolation and software compartmentalisation; and safe interoperation between managed languages and native-code extensions. Prototyped via hardware-software co-design, and evaluated on FPGA over a six-year period with support from DARPA , the CHERI processor is able to run adapted versions of the FreeBSD operating system (CheriBSD) and open-source application stack, and is targeted by an extended version of the Clang/LLVM compiler. This talk introduces the CHERI architecture and potential applications, and will also describe current research directions.

This talk is part of the Wednesday Seminars - Department of Computer Science and Technology series.

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