Hypervisor Scheduler Enhancement Using OS-Hardware Interactions

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• Hwanju Kim, KAIST
• Wednesday 27 March 2013, 10:00-11:00
• Small Lecture Theatre, Microsoft Research Ltd, 21 Station Road, Cambridge, CB1 2FB.

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As the hypervisor has become a common software layer in conventional software stack and applications are continuously diversifying, computing environments have now undergone increasing gap between end-user software and underlying hardware. In particular, the design principle of lightweight hypervisor causes a blockage to information flow while granting the workload-agnostic hypervisor the entire control of bare-metal hardware resources. The blockage leads the hypervisor to ineffective decisions about CPU resource scheduling, which is a primitive role of arbitrating the competing demands of workload executions, due to the lack of workload information. In this talk, I present two CPU scheduling approaches devised to improve the performance of consolidated workloads using common OS-hardware interactions: 1) Demand-based coordinated scheduling for SMP V Ms, and 2) task-aware scheduling for I/O-intensive and interactive workloads. Firstly, the demand-based coordinated scheduling addresses scheduling issues arising when communication-intensive workloads are hosted on multiprocessor VMs, which share underlying multi-core processors. Inspired by the demand-based coscheduling demonstrated in cluster environments, I devised an SMP VM scheduling scheme that dynamically coordinates vCPUs based on their communication (i.e., inter-processor interrupt). Secondly, task-aware VM scheduling makes a task-oblivious hypervisor scheduler aware of task-level characteristics such as I/O-boundness and user interactivity. To this end, I devised several inference techniques based on per-task CPU time and I/O events that can be captured by OS-hardware interactions.

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