Performance Comparisons of Hard Logic, Programmable Soft Logic, and Instruction Set Architectures

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• Jonathan Rose - University of Toronto
• Wednesday 09 December 2009, 14:15-15:15
• Lecture Theatre 1, Computer Laboratory.

If you have a question about this talk, please contact Mateja Jamnik.

Note unusual out of term date.

The excitement and creativity in the field of computing has been enabled by the exponential progress of the underlying circuit fabrication technology. Despite this, it is rare that researchers (or industry) create their own chips because it is simply too difficult and expensive, but rather use programmable pre-fabricated instruction set processors.

The other widely-used way of leveraging the underlying chip fabrication technology is to employ Field-Programmable Gate Arrays (FPGAs) which are made of fine-grained units of logic and memory that can be programmably interconnected at the electrical level, bit-wise.

FPG As and instruction set processors are capable of implementing similar things, but each has different strengths as measured by cost, speed, energy consumption and ease of use. In this talk, I will present an overview of several research projects that compare FPGA cost, performance and power consumption against other implementation ‘media’:

1. Hard, fully-fabricated integrated chips (often referred to as ASI Cs).
2. High-performance uniprocessors.
3. General Purpose Graphics Processing Units (GP GPUs).
4. Soft Processors and Soft Vector Processors (processors built on top of FPGA fabrics)

Although these were independent comparisons (each driven by different applications), I will also try to glue them together and see how the results reflect the strengths and weaknesses of each computation medium, and discuss the implications for future directions in programmable architectures.

This talk is part of the Wednesday Seminars - Department of Computer Science and Technology series.

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