University of Cambridge > > Wednesday Seminars - Department of Computer Science and Technology  > Coherence Attacks and Defenses in 2.5D Integrated Systems

Coherence Attacks and Defenses in 2.5D Integrated Systems

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  • UserProfessor Paul Gratz - Professor in the Department of Electrical and Computer Engineering, Texas A&M University. Visiting academic at the Department of Computer Science and Technology, University of Cambridge
  • ClockWednesday 08 November 2023, 15:05-15:55
  • HouseLecture Theatre 1, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Ben Karniely.

Abstract: Industry is moving towards large-scale hardware systems which bundle processor cores, memories, accelerators, etc. via 2.5D integration. These components are fabricated separately as chiplets and then integrated using an interconnect carrier, i.e., an interposer. This new design style is beneficial in terms of yield and economies of scale, as chiplets may come from various vendors and are relatively easy to integrate into one larger sophisticated system. However, the benefits of this approach come at the cost of new security and integrity challenges, especially when integrating chiplets that come from not fully trusted, third-party vendors.

In this talk, I explore these challenges for modern interposer-based systems of cache-coherent, multi-core chiplets. First, I will present a new form of coherence-oriented hardware Trojan attacks, that pose a significant threat to chiplet-based designs and demonstrate how these basic attacks can be orchestrated to pose a significant threat to interposer-based systems. Second, I will show our proposal for a novel scheme using an active interposer as a generic, secure-by-construction platform that forms a physical root of trust for modern 2.5D systems. The implementation of our scheme is confined to the interposer, resulting in little cost and leaving the chiplets and coherence system untouched. I will show that our scheme prevents a range of coherence attacks with low overheads on system performance, ~4%. Overheads reduce as workloads increase, ensuring the scheme’s scalability.

Bio: Paul V. Gratz is a Professor in the department of Electrical and Computer Engineering at Texas A&M University. His research interests include efficient and reliable design in the context of high performance computer architecture, processor memory systems and on-chip interconnection networks. He received his B.S. and M.S. degrees in Electrical Engineering from The University of Florida in 1994 and 1997 respectively. From 1997 to 2002 he was a design engineer with Intel Corporation. He received his Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2008. His paper, “Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom,” was selected as a Top Pick from the architecture conferences in 2018 by IEEE Micro. His papers “Path Confidence based Lookahead Prefetching” and “B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors” were nominated for best papers at MICRO ‘16 and MICRO ‘14 respectively. At ASPLOS ‘09, Dr. Gratz received a best paper award for “An Evaluation of the TRIPS Computer System.” In 2016 he received the “Distinguished Achievement Award in Teaching – College Level” from the Texas A&M Association of Former Students and in 2017 he received the “Excellence Award in Teaching, 2017” from the Texas A&M College of Engineering.

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This talk is part of the Wednesday Seminars - Department of Computer Science and Technology series.

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