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CAS FPGA Talks

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FPGA -related talks in the CAS Group at IC

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If you have a question about this list, please contact: Dr George A Constantinides; Alastair Smith. If you have a question about a specific talk, click on that talk to find its organiser.

0 upcoming talks and 46 talks in the archive.

What is Web 2.0 and how it changes almost everything!

UserAntonio Roldao (PhD@IC).

HouseRoom 611, EEE.

ClockThursday 14 May 2009, 14:30-15:30

TIADC Mismatch Compensation

UserProf Lim Yong Ching (Nanyang Technological University, Singapore).

HouseRoom 611, EEE.

ClockThursday 14 May 2009, 11:00-12:00

Parallel Computation of the Phylogenetic Likelihood Kernel in HW and SW

UserDr. Alexandros Stamatakis, Exelixis Lab, Department of Computer Science, Technische Universität München.

HouseMahanakorn Laboratory, EEE.

ClockTuesday 31 March 2009, 14:30-15:30

Static scheduling of SDRAM commands using constraint logic programming

UserSam Bayliss (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockWednesday 25 March 2009, 12:00-13:00

ARC: Practice Talk 2

UserAsma Kahoul (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 12 March 2009, 12:00-13:00

ARC Preview: Heterogeneous Architecture Exploration: Analysis vs Parameter Sweep

UserAsma Kahoul (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 05 March 2009, 15:00-15:30

Challenges in FPGA Research

UserDr Peter Jamieson (Imperial College).

HouseMahanakorn Laboratory, EEE.

ClockThursday 26 February 2009, 12:00-13:00

Multiplication Without Multipliers: Algorithms, Applications, and Extensions

UserDr Oscar Gustafsson (Linköping University).

HouseMahanakorn Laboratory, EEE.

ClockFriday 20 February 2009, 12:00-12:45

Predicting minimal error bounds through an algorithm

UserDavid Boland ( Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 19 February 2009, 12:00-13:00

Challenges in FPGA Research

UserDr Peter Jamieson (Imperial College).

HouseMahanakorn Laboratory, EEE.

ClockThursday 19 February 2009, 12:00-13:00

Fixed-Point Arithmetic in DSP

UserDr George A Constantinides (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 22 January 2009, 16:00-17:00

FPGA architecture optimisation using geometric programming

UserAlastair Smith (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 22 January 2009, 12:00-13:00

Transforming image processing algorithms for efficient FPGA implementation

UserDonald Bailey, Massey University, New Zealand.

HouseMahanakorn Laboratory, EEE.

ClockWednesday 21 January 2009, 11:00-12:00

FPT Report-Back

UserAntonio Roldao (PhD@IC).

HouseRoom 611, EEE.

ClockWednesday 17 December 2008, 15:00-15:30

Best Papers of Autumn Term

UserSeveral.

HouseRoom 611, EEE.

ClockWednesday 17 December 2008, 14:00-15:00

'A linear algebra framework for automatic determination of optimal data layouts' by Mahmut Kandemir et al.

UserSam Bayliss (Imperial College London).

House503, EEE.

ClockWednesday 17 December 2008, 12:00-12:30

Heterogeneous Architecture Exploration: Analysis vs. Parameter sweep

UserAsma Kahoul (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockMonday 01 December 2008, 12:00-13:00

(FPT Preview) Optimizing Coarse-Grained Units in Floating Point Hybrid FPGAs

UserChi Wai Yu, Department of Computing, Imperial College London.

HouseMahanakorn Laboratory, EEE.

ClockFriday 28 November 2008, 16:00-16:30

(FPT Preview) Modelling and Compensating for Clock Skew Variability in FPGAs

UserDr Pete Sedcole (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockFriday 28 November 2008, 15:30-16:00

(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining

UserKieron Turkington (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockFriday 28 November 2008, 11:00-12:00

(FPT Preview) A Scalable FPGA Architecture for Non-linear SVM Training

UserMarkos Papadonikolakis (Imperial College).

HouseMahanakorn Laboratory, EEE.

ClockFriday 28 November 2008, 11:00-12:00

CG: Optimizing FPGA Speed using Custom Precision

UserAntonio Roldao (PhD@IC).

HouseMahanakorn Laboratory, EEE.

ClockWednesday 19 November 2008, 14:00-15:00

Improving Real-time Observability in Embedded Logic Analysis

UserNicola Nicolici (McMaster University, Canada).

HouseRoom 611, EEE.

ClockFriday 07 November 2008, 16:00-17:00

COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip

UserProf Nikil Dutt (University of California, Irvine).

HouseRoom 611, EEE.

ClockFriday 07 November 2008, 11:30-12:30

On Logical Masking Effects of Soft Errors

UserProf. Sudhakar M. Reddy (University Of Iowa, USA).

HouseRoom 611, EEE.

ClockFriday 07 November 2008, 10:30-11:30

A New Approach for Exploring Numerical Accuracy

UserDavid Boland ( Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockMonday 03 November 2008, 12:00-13:00

Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural Development

UserAlastair Smith (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockMonday 20 October 2008, 12:00-13:00

Accelerating Iterative Methods Using FPGAs

UserAntonio Roldao (PhD@IC).

HouseMahanakorn Laboratory, EEE.

ClockTuesday 07 October 2008, 14:00-15:00

Developing analytical techniques for FPGA architecture design

UserAlastair Smith (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockMonday 06 October 2008, 11:00-12:00

Some Ideas from my Sabbatical

UserDr George A Constantinides (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockWednesday 24 September 2008, 10:00-11:00

Fault Tolerance and Reliability in FPGAs

UserEdward Stott (Imperial College).

HouseMahanakorn Laboratory, EEE.

ClockWednesday 20 August 2008, 14:00-15:00

Memory and Datapath optimisation for FPGA co-processors

UserKieron Turkington (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockThursday 14 August 2008, 14:00-15:00

Four Important Concepts to Consider when Using Multicore Clusters

UserDr George A Constantinides (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockMonday 11 August 2008, 11:30-12:30

An FPGA-based Implementation of the MINRES Algorithm

UserDavid Boland, Imperial College London.

HouseMahanakorn Laboratory, EEE.

ClockTuesday 05 August 2008, 11:30-12:15

Report from RSSI

UserDavid Boland ( Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockTuesday 15 July 2008, 15:00-15:30

Low-Power Design for Reconfigurable Computing

UserDr George A Constantinides (Imperial College London).

HouseMahanakorn Laboratory, EEE.

ClockTuesday 15 July 2008, 11:30-12:30

Investigating I/O & Memory Bandwidth trade-offs for Iterative Algorithms’

UserDavid Boland, Imperial College London.

HouseMahanakorn Laboratory, EEE.

ClockThursday 03 July 2008, 12:00-13:00

From the Horse's Mouth - Architecture of Stratix III

UserVaughn Betz, Altera Corp.

HouseRoom 611, EEE.

ClockTuesday 01 July 2008, 11:00-12:00

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