Transforming image processing algorithms for efficient FPGA implementation

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• Donald Bailey, Massey University, New Zealand
• Wednesday 21 January 2009, 11:00-12:00
• Mahanakorn Laboratory, EEE.

If you have a question about this talk, please contact Alastair Smith.

Synopsis: FPG As are increasingly being used as an implementation platform for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. However many designs do not realise their full potential because many current techniques are optimized for implementation on serial computers. Efficient implementation requires transforming the algorithm and mapping it to a corresponding architecture. This process is illustrated with connected components analysis, a step common to many image processing applications. Standard connected components analysis methods divides the process into two distinct steps: connected component labelling, followed by analysis of the resultant connected components. Connected components labelling requires 2 passes through the image, and analysis requires at least one further pass. When implemented on an FPGA , this requires frame buffer memories, and introduces considerable latency. Careful analysis of the problem shows that the labelling and analysis stages may be pipelined, and the frame buffer eliminated. The result is a single pass algorithm. This algorithm is further transformed to reduce the memory requirements, and reduce the latency further. The result is an efficient algorithm that is able to directly process images streamed from a camera.

Biography: Donald G Bailey received the B.E. (Hons) degree in Electrical Engineering in 1982, and the PhD degree in Electrical and Electronic Engineering from the University of Canterbury, New Zealand in 1985. From 1985 to 1987, he applied image analysis to the wool and paper industries within New Zealand. From 1987 to 1989 he was a Visiting Research Engineer at University of California at Santa Barbara. Dr Bailey joined Massey University in Palmerston North, New Zealand as Director of the Image Analysis Unit at the end of 1989. He is currently an Associate Professor in the School of Engineering and Advanced Technology, and leader of the Image and Signal Processing Research Group. His primary research interests include applications of image analysis, machine vision, and robot vision. One area of particular interest is the application of FPG As to implementing image processing algorithms.

This talk is part of the CAS FPGA Talks series.

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• CAS FPGA Talks
• Mahanakorn Laboratory, EEE

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