Abstract

This paper proposes a novel test method for measuring the worst case path delay of any circuit on an FPGA , combinatorial or sequential, where little prior knowledge of the circuit’s internal structure is required. The method is based on detecting changes in the transition probability profile on the circuit’s output nodes while a range of test clock frequencies is stepped through. The method is applied to three classes of circuits, all implemented on an Altera Cyclone III FPGA : an adder carry chain, an embedded multiplier and a linearfeedback shift-register. The measured delays are compared to that found by a previously published, but much more time consuming, method and their results match to within 12%.