Post-Silicon Validation: New Frontiers for Formal Verification Research

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• Alan Hu, University of British Columbia
• Wednesday 21 July 2010, 11:00-12:00
• Small public lecture room, Microsoft Research Ltd, 7 J J Thomson Avenue (Off Madingley Road), Cambridge.

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Abstract: Post-silicon validation is the problem of determining whether a new design, as fabricated in silicon, behaves according to its specification. As such, post-silicon validation shares attributes with pre-silicon design verification (which seeks to find bugs in the design before it has been fabricated), as well as manufacturing test (which seeks to find manufacturing defects during high-volume production of chips). Post-silicon validation currently consumes a large fraction of the total verification schedule on typical large designs, and the problem is growing worse. Even worse, the schedule variability is greatest post-silicon, creating unacceptable uncertainty in time-to-market.

The post-silicon validation problem has unique features and challenges that create new questions and problems for formal verification research. In this talk, I will survey the problem space, present a bit more depth on some recent work applying formal techniques to post-silicon validation, and suggest some areas where I believe formal techniques hold great promise.

Biography: Alan J. Hu received his BS and PhD degrees from Stanford University. He is a Professor and former Associate Head in the Computer Science Department at the University of British Columbia. For 20 years, his main research focus has been automated, practical techniques for formal verification. He has served on the program committees of all major CAD and formal verification conferences, and chaired or co-chaired CAV (1998), HLDVT (2003), FMCAD (2004), and HVC (2008). He was also a Technical Working Group Key Contributor on the 2001 International Technology Roadmap for Semiconductors, and is a member of the Technical Advisory Board of Jasper Design Automation.

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