P4-NetFPGA

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• Stephen Ibanez (Stanford University)
• Thursday 20 April 2017, 15:00-16:00
• FW26, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Liang Wang.

Today, P4 is the leading high level programming language for expressing how packets are processed by the data-plane of any programmable packet processing device. There have already been many new and exciting applications proposed at top networking conferences, such as SIGCOMM , which take advantage of data-plane programmability. Unfortunately, it has been a significant challenge for researchers to test their P4 programs in real hardware at line-rate. In this talk, I will introduce the P4-NetFPGA workflow, which uses the Xilinx P4-SDNet toolchain and is designed to make it easy for researchers to compile their P4 programs to the NetFPGA SUME board, thus facilitating hardware testing. NetFPGA is an open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems and is the de-facto experimental platform for line-rate implementations of network research. I will conclude with a discussion about the future research direction for the P4-NetFPGA workflow.

Bio: Stephen Ibanez is a PhD Candidate at Stanford working with Professor Nick McKeown. His research interests involve finding new and exciting applications for programmable data-planes, running P4 programs on programmable hardware, network measurement and management, as well as network security. He has experience using P4 to design switches that implement proactive congestion control algorithms for next generation datacenter networks. Stephen is leading the effort to bring together a community of developers and users for the P4-NetFPGA platform. He has performed demos at SIGCOMM as well as at numerous P4 Workshops.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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