University of Cambridge > > Computer Laboratory Digital Technology Group (DTG) Meetings > The Next-Generation Vector Architecture for HPC

The Next-Generation Vector Architecture for HPC

Add to your list(s) Download to your calendar using vCal

If you have a question about this talk, please contact Alastair Beresford.

ARM ’s next-generation vector architecture known as the Scalable Vector Extension (SVE) has been created primarily for energy-efficient high-performance computing (HPC) designs. SVE has emerged as a key ingredient in the race towards Exascale computing and has features aimed at meeting the ever-increasing computing demands of scientific research in domains such as meteorology, astronomy, quantum physics, and fluid dynamics.

In this presentation, I will go through the design of the SVE architecture, from the set of design requirements and constraints to various instruction set components. I will explain why a Vector-Length-Agnostic approach was adopted in the design of the architecture and how it works in practice. I will also explain results obtained from measuring the performance of critical kernels taken from standard HPC benchmark suites, and highlight any scalability issues that were encountered.

Bio: Mbou Eyole is a processor research engineer at ARM . He is responsible for creating next-generation architectures and has been a key contributor to ARM ’s new vector architecture called the Scalable Vector Extension. He is a Chartered Engineer and has filed over 14 patents on CPU architectures, instruction set extensions, and microarchitectures. His research focuses on improving the applicability of SIMD architectures to a broader range of workloads which have high computational demands. In particular, he wrestles with the problem of irregular computation pathways and non-affine memory accesses in parallel workloads. He also has significant experience in sensor network design and in his PhD (University of Cambridge, 2008) he proposed a multi-layered decentralised model of distributed computation with energy-efficient multicore nodes managing sub-clusters of sensor nodes. Before joining ARM , he was a Research Fellow at Trinity College, Cambridge, where he investigated scheduling in massively parallel architectures.

This talk is part of the Computer Laboratory Digital Technology Group (DTG) Meetings series.

Tell a friend about this talk:

This talk is included in these lists:

Note that ex-directory lists are not shown.


© 2006-2022, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity