University of Cambridge > > Computer Laboratory Systems Research Group Seminar > High-level development and debugging of FPGA-based network programs

High-level development and debugging of FPGA-based network programs

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If you have a question about this talk, please contact Liang Wang.

Field-Programmable Gate Arrays (FPGAs) are a form of reconfigurable computing device that continues to gain popularity in various environments, most recently datacentres. The principal difficulty with using FPG As is that they require a radically different mindset and tooling when compared to programming more mainstream devices such as CPUs and GPUs.

In this talk I’ll describe some contributions and ongoing work of the Network-as-a-Service project ( First I’ll describe the Emu system, which seeks to harmonise the CPU - and FPGA -programming mindsets by facilitating the use of C# to write network programs that can run on either device. Emu provides (i) a workflow and library support for the Kiwi HLS compiler to facilitate the development of network programs to run on FPG As, and (ii) the Pax system ( using which the same network programs can be run on CPUs with minimal changes.

Second I’ll describe “Program-hosted Directability” (PhD), a method to transform programs to improve their debuggability. Programs running on FPG As are afforded frugal and ad hoc debugging support, and need to have debugging features compiled-in. PhD uses a minimal controller language to implement various debugging features, which enables run-time reconfigurability of debug features.

This work builds on the Kiwi HLS compiler ( and NetFPGA SUME (, and is the fruit of collaboration with Pietro Bressana, Richard Clegg, Paolo Costa, Jon Crowcroft, Salvator Galea, David Greaves, Luo Mai, Andrew W Moore, Richard Mortier, Peter Pietzuch, Jonny Shipton, Robert Soule, Marcin Wojcik, and Noa Zilberman.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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