The Future of Computer Architecture

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• Gavin Stark, Visiting Fellow, Computer Laboratory
• Tuesday 29 November 2016, 15:00-16:30
• SW01, Computer Laboratory.

If you have a question about this talk, please contact Robert Mullins.

The silicon industry is struggling to push process technology to get smaller, faster transistors, and the past trajectory is not being followed. It is also struggling, though, in making use of the transistors that it can produce today. It is not unreasonable to suggest 10 billion transistor devices in 14nm, and there may come a point where 100 billion transistors can be used in a single die; coupling multiple dice will provide even larger problems. So even without a reignition of Moore’s Law, computer architecture has real problems to solve, and these are not necessarily being addressed today.

Consider also that computer architecture has two masters to please – the hardware engineers that must make it a reality, and the software engineers that must make use of it; and further, that software engineering struggles to develop use of computer architecture that has not been realized in hardware – there can be a large time gap between evolutionary architectural steps and their benefit.

In this seminar I will cover the scale of the architectural problem, some of the physical limitations that silicon engineers face, and the subsequent opportunities for innovation (and some pointers on how to progress…).

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Gavin Stark is a Visiting Fellow at the Computer Laboratory and is responsible for silicon architecture and Netronome, a high speed communications processing company. He read CompSci at Cambridge, before working at Acorn Computers at the birth of ARM , returning to do a PhD in communications with Prof. Hopper. Starting a career in silicon design and architecture at Virata and then Cirrus Logic, he led Basis Communications as CTO before its acquisition be Intel in 2000. Leaving Intel in 2003, he returned to Cambridge in 2006 and took on silicon architecture at Netronome. Through the years he has architected and designed six generations of network processors, the latest supporting hundreds of cores in 22nm designs with billions of transistors.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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