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Synthesizing Accelerators for FPGAs the Functional Way

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If you have a question about this talk, please contact Timothy M Jones.

FPG As (Field Programmable Gate Arrays) have become the substrate of choice to implement accelerators. They deliver high performance with low power consumption, while offering the flexibility of being re-programmable. But they are notoriously hard to program directly using HDLs (Hardware Description Languages). Traditional HLS (High-Level Synthesis) are far from being perfect as programmers are still required to write hardware-specific code and existing HLS tools often produce suboptimal designs.

This talk will present current efforts to address these shortcomings, using a multi-level functional IR (Intermediate Representation). As we will see, a functional IR makes optimizations via rewrite rules simple to express, and abstract away the hardware details. This approach has the advantage of generating high performance designs in a predictable way, drastically reducing design time. This talk will show how neural networks are easily represented using functional hardware-agnostic constructs. The resulting FPGA synthesized designs achieve near-peak performance and are competitive with the output produced by current HSL tools.

Christophe Dubach is an Associate Professor jointly appointed in the department of Electrical and Computer Engineering (ECE) and the school of Computer Science (CS) at McGill University. He also holds a Canada CIFAR AI Chair at Mila. Up until 2019, he was a Reader (Associate Professor) at the University of Edinburgh. He received a PhD in Informatics from the University of Edinburgh in 2009 and an MSc degree in Computer Science from EPFL in 2005. In 2010, he spent one year as a visiting researcher at the IBM Watson Research Center (USA) working on the LiquidMetal project. His current research interests include high-level programming models for heterogeneous systems, co-design of both computer architecture and optimising compiler, high-level synthesis, and the application of machine learning to these areas.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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