University of Cambridge > Talks.cam > Computer Laboratory Computer Architecture Group Meeting > G: A high-level packet processing language with a high-speed FPGA-based implementation

G: A high-level packet processing language with a high-speed FPGA-based implementation

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As the Internet evolves, it is becoming increasingly necessary to provide multiple packet processing solutions, in order to support diversity and innovation both in services and in underlying infrastructure. In turn, there is a requirement for supplying underlying high-performance network node architectures that support flexibility, scalability, concurrency, and diversity. This talk will discuss modern Field Programmable Gate Array (FPGA) devices as a natural technology for the necessary high-speed programmable packet processing nodes. It will introduce G, an experimental high-level packet-centric language for describing packet processing specifications in an implementation-independent manner. G can be compiled to give high-speed FPGA -based components that can be assembled alongside other components to build network nodes, framework based on the MIT Click modular approach. Compilation involves generating virtual processing architectures tailored to specific packet processing requirements. Some examples (including MPLS and carrier Ethernet) will be presented to illustrate the performance obtainable from G solutions, and the ease of experimentation with both packet processing requirements and implementation characteristics. The results to date indicate that FPGA devices can be programmed in a high-level manner attractive to the networking specialist, without seriously compromising their raw capabilities.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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