Architectural Impacts of the Silicon Performance Wall

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• Dr Gavin Stark - Netronome and Visiting Industrial Fellow, Computer Laboratory.
• Wednesday 30 November 2016, 16:15-17:15
• Lecture Theatre 1, Computer Laboratory.

If you have a question about this talk, please contact David Greaves.

Mainstream CPU clock speeds have barely increased in the past ten or more years, and the march of new process technologies has slowed – silicon is no longer getting faster automatically, and the free lunches that semiconductor engineers used to get thanks to manufacturing technology are not quite so free. This is not to say that nothing has changed for the better as process technology has moved from 0.18um to 14nm – transistor budgets have gone up considerably, to start with.

These issues have been part of the reality underlying architecture and design decisions for silicon engineers. In this talk I will provide an insider’s view into some of these challenges, and look at the evolution of architectural choices across a family of memory-centric processors built on leading edge Intel technology through the years.

This talk is part of the Wednesday Seminars - Department of Computer Science and Technology series.

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