Concurrent Algorithms for Emerging Hardware Platforms

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• Irina Calciu, Brown University
• Thursday 12 February 2015, 09:00-10:00
• Indigo Meeting room, Microsoft Research Ltd, 21 Station Road, Cambridge, CB1 2FB.

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Computer architecture has recently seen an explosion of innovation that has enabled more parallel execution. The number of computing cores used in every area of the software ecosystem continues to increase, and parallelism within programs is now ubiquitous. Ideally, performance would scale linearly with the number of cores, but in practice that is rarely the case. Communication and synchronization between cores running the same application are often necessary, but usually come at a high cost. This results in negative scalability and a significant drop in performance. In this context, parallel software needs to provide more simplified programming patterns and tools that enable a higher potential for parallelism without increasing the burden on the programmer. In this talk, I will discuss new techniques to simplify writing efficient parallel code that leverage novel architectural features from many current systems. First, I will describe programming abstractions, such as delegation, elimination, combining and transactional memory, which improve scalability and performance of concurrent programs. I will then present a new concurrent priority queue design that is based on these abstractions and is significantly faster than prior implementations. Finally, I will describe Invyswell, a new hybrid transactional memory that combines Intel’s Restricted Transactional Memory capability with a software transactional memory to guarantee efficient execution and forward progress of transactional programs. Developers can use all of these abstractions as building blocks to create efficient code that is able to scale on very diverse platforms, without requiring specialized knowledge of parallel programming.

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