Compile-time Instruction Scheduling for Modern ARM Processors - Low Level Design Enabling Performance In High Level Applications

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• James Greenhalgh, ARM
• Friday 28 November 2014, 13:15-00:00
• FW11, Computer Laboratory.

If you have a question about this talk, please contact Jan Samols.

The vast majority of software is written at high levels of abstraction from the hardware. This talk will shed light on the translation layers and hardware design considerations that enable applications to run at high performance on modern ARM processor designs.

Static Instruction scheduling is a compiler optimisation developed in the 1980’s to increase processor resource usage in superscalar and pipelined processor designs. While many modern processors are out-of-order, and therefore able to dynamically schedule instructions, ARM processor technology is used in a huge number of markets, each with unique design constraints. In this talk, we will introduce and compare the top-level pipeline designs of contemporary ARM processors, show where static instruction scheduling is beneficial, and detail the algorithms used by the GCC and LLVM compilers to perform instruction scheduling.

This talk will also include a brief general introduction to ARM , and an opportunity for specific and general Q&A.

This talk is part of the Technical Talks - Department of Computer Science and Technology series.

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