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Towards Zero Latency Photonic Switching

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Developments in silicon photonics could see photonic network elements co-packaged with processors creating low energy networks-on-chip (NoC) or direct links between processors across a data centre. However, although it is easy to show that basic photonic network elements have lower latency and energy requirements than their electronic counterparts, on the system level the issue is not so clear cut. For example, the scheduling overhead incurred in reconfiguring photonic switches can be a significant overhead for the short messages created by shared memory networks and Ethernet. Furthermore, recent NoC results have suggested that the edge buffering required in photonic networks results in greater overall energy consumption than electronic NoCs. Due to the fundamental differences between electronic and photonic networks, new architectures and scheduling algorithms are required to exploit photonics in future systems. This talk will describe low energy, low latency network architectures for two scenarios: (1) a shared memory coherence network for cache coherent multicore chips or multi-socket servers; (2) an optical top-of-rack switch for data centres.

This talk is part of the Microsoft Research Cambridge, public talks series.

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