Hardware Neural Network Accelerators

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• Olivier Temam, Inria
• Thursday 05 December 2013, 14:00-15:00
• Auditorium, Microsoft Research Ltd, 21 Station Road, Cambridge, CB1 2FB.

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As architectures evolve towards heterogeneous multi-cores composed of a mix of cores and accelerators, designing accelerators which realize the best possible tradeoff between flexibility and efficiency is becoming a prominent issue. The first question is for which category of applications one should primarily design accelerators ? Together with the architecture trend towards accelerators, a second simultaneous and significant trend in high-performance and embedded applications is developing: many of the emerging high-performance and embedded applications rely on machine-learning techniques. This trend in application comes together with a third and equally remarkable trend in machine-learning where a small number of techniques, based on neural networks, have been proved in the past few years to be state-of-the-art across a broad range of applications. As a result, there is a unique opportunity to design accelerators which can realize the best of both worlds: significant application scope together with high performance and efficiency due to the limited number of target algorithms. Moreover, the inherent robustness of neural networks can be leveraged to design accelerators which are also tolerant to defects and transient faults. I will discuss the opportunity to integrate such accelerators in computing systems, present several accelerators we have designed in the past few years, and the performance, energy and fault-tolerance benefits they can bring.

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