On the efficient implementation of large round-robin arbiters

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• Emanuel Savin (Intel)
• Thursday 18 April 2013, 10:00-11:00
• FW11, Computer Laboratory.

If you have a question about this talk, please contact Eiko Yoneki.

This talk describes a binary-tree search architecture for round-robin arbiters (RRA), suitable for efficient implementations of resource schedulers for L2/L3 switch ASI Cs. The RRA architecture comprises two main components: 1) a priority-select block, which consists of a tree of OR-gates selecting maximum values across various segments of the binary-request vector, and 2) a grant-select module, which employs a unit-weighted representation of the priority index. The proposed design is compared with a conventional crossbar fabric arbiter used in the Tiny Terra project, and shown to provide significant improvements on both latency as well as gate-counts. The gate-count improvement is achieved by sharing the same grant-select module for two priority-encoder units, while the overall delays are reduced through the use of a united-weighted priority index. A possible extension of the proposed architecture to the implementation of arbiters with selection mechanisms designed to extract a 2nd (or n-th) highest priority active request, is also suggested.

Bio: C. Emanuel Savin is a staff engineer with Intel Corp., in Swindon. He has a Ph.D. degree from Concordia University in Montreal, Canada, and his field of interest is in the area of hardware architectures for router components and signal processing applications, and the related implementation methodologies targeting ASI Cs and FPG As.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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