Seamless Clock Synchronization under Migration

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• Darryl Veitch (University of Melbourne)
• Thursday 17 June 2010, 16:00-17:00
• FW26, Computer Laboratory, William Gates Builiding.

If you have a question about this talk, please contact Eiko Yoneki.

I will describe recent work on a new timekeeping architecture for virtualized systems, in the context of Xen. Built upon a feed-forward based RADclock synchronization algorithm, it ensures that the clocks in each OS sharing the hardware derive from a single central clock in a resource effective way, and that this clock is both accurate and robust. A key advantage is simple, seamless migration with consistent time. We also provide a detailed examination of the HPET and Xen Clocksource counters. All results are validated using a careful methodology in a hardware supported testbed.

Bio: Darryl Veitch completed a BSc._Hons.at Monash University, Australia (1985) and a mathematics Ph.D.~from DAMPT , Cambridge (1990). He worked at TRL (Telstra, Melbourne), CNET (France Telecom, Paris), KTH (Stockholm), INRIA (Sophia Antipolis, France), Bellcore (New Jersey), RMIT (Melbourne) and EMUlab and CUBIN at The University of Melbourne, where he is a Principal Research Fellow. He is currently on sabbatical with INRIA and Technicolor in Paris, France. His research interests are in computer networking and include traffic modelling, parameter estimation, active measurement, traffic sampling, and clock synchronisation over networks. He is a Fellow of the IEEE .

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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