Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips / Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures.

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• Giray Yağlıkçı / Geraldo Francisco
• Thursday 14 March 2024, 15:00-16:00
• FW26.

If you have a question about this talk, please contact Ryan Gibb.

Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips

DRAM is the prevalent main memory technology due to its high density and low latency characteristics. The increasing need for faster access rates and larger DRAM capacity motivates improving the DRAM chip density. Manufacturing technology node size shrinks over DRAM chip generations to provide higher DRAM chip density. This technology scaling causes DRAM cell size and cell-to-cell distance to reduce significantly. As a result, DRAM cells become more vulnerable to read disturbance, i.e., accessing a DRAM cell disturbs data stored in another physically nearby cell.

To provide a deeper understanding of and solutions to DRAM read disturbance, we 1) conduct experimental studies on real DRAM chips where we investigate the effects of temperature, access patterns, intra-chip variations, and wordline voltage; and 2) propose architecture-level solutions to mitigate DRAM read disturbance while it is exacerbated by technology node scaling and existing mitigations face practicality challenges due to a fundamental need for exposing proprietary information. This talk will provide a summary of these works.

Bio: Giray is a Ph.D. candidate in the Safari Research Group at ETH Z ürich, working with Prof. Onur Mutlu. His current broader research interests are in computer architecture, systems, and hardware security with a special focus on DRAM robustness and performance. In particular, his PhD research focuses on understanding and solving DRAM read disturbance vulnerability. Giray has published several works on this topic in major venues such as HPCA , MICRO, ISCA , DSN, and SIGMETRICS . One of these works, BlockHammer, was named as a finalist by Intel in 2021 for the Intel Hardware Security Academic Award. Giray’s research is in part supported by Google and the Microsoft Swiss Joint Research Center.

Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures.

The increasing prevalence and growing size of data in modern applications have led to high costs for computation in traditional processor-centric computing systems. Moving large volumes of data between memory devices (e.g., DRAM ) and computing elements (e.g., CPUs, GPUs) across bandwidth-limited memory channels can consume more than 60% of the total energy in modern systems. To mitigate these costs, the processing-in-memory (PIM) paradigm moves computation closer to where the data resides, reducing (and in some cases eliminating) the need to move data between memory and the processor. There are two main approaches to PIM : (1) processing-near-memory (PnM), where PIM logic is added to the same die as memory or to the logic layer of 3D-stacked memory; and (2) processing-using-memory (PuM), which uses the operational principles of memory cells to perform computation.

Many works from academia and industry have shown the benefits of PnM and PuM for a wide range of workloads from different domains. However, fully adopting PIM in commercial systems is still very challenging due to the lack of tools and system support for PIM architectures across the computer architecture stack, which includes: (i) workload characterization methodologies and benchmark suites targeting PIM architectures; (ii) frameworks that can facilitate the implementation of complex operations and algorithms using the underlying PIM primitives; (iii) compiler support and compiler optimizations targeting PIM architectures; (iv) operating system support for PIM -aware virtual memory, memory management, data allocation, and data mapping; and (v) efficient data coherence and consistency mechanisms. Our goal in this talk is to highlight tools and system support for PnM and PuM architectures that aim to ease the adoption of PIM in current and future systems.

Bio: Geraldo F. Oliveira is a Ph.D. candidate in the Safari Research Group at ETH Z ürich, working with Prof. Onur Mutlu. His current broader research interests are in computer architecture and systems, focusing on memory-centric architectures for high-performance and energy-efficient systems. In particular, his Ph.D. research focuses on taking advantage of new memory technologies to accelerate distinct classes of applications and provide system support for novel memory-centric systems. Geraldo has published several works on this topic in major conferences and journals such as HPCA , ASPLOS, ISCA , MICRO, and IEEE Micro.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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