|COOKIES: By using this website you agree that we can place Google Analytics Cookies on your device for performance monitoring.|
Motivating Future Interconnects: A Differential Measurement Analysis of PCI Latency
If you have a question about this talk, please contact Eiko Yoneki.
Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and packaging mean that further advances will require a new approach to interconnect design. Although latency in networks has been the focus of the High-Performance Computing architect and of concern across the computer community, we illustrate how an evolution in the common PCI interconnect architecture has worsened latency by a factor of between 3 and 25 over earlier incarnations.
This talk is part of the Computer Laboratory Systems Research Group Seminar series.
This talk is included in these lists:
Note that ex-directory lists are not shown.
Other listsHEP phenomenology joint Cavendish-DAMTP seminar DAMTP Friday GR Seminar History of Medicine Seminars
Other talksUnorthodox Interactions at Work Structure, Biology and Therapeutic Potential of Novel ER Located Growth Factors Limits of some combinatorial problems Mixed Methods for Two-Phase Darcy-Stokes Mixtures of Partially Melted Materials with Regions of Zero Porosity Towards a theory of layered neural circuit architectures Microglia proliferation in health and disease