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Improving Cache Performance while Mitigating Software Side-Channel Attacks
If you have a question about this talk, please contact Joseph Bonneau.
Improving the security of computers has traditionally been associated with degrading performance. Princeton researchers show a rather surprising result where both security and performance can be improved by rethinking cache architecture. Cache subsystems bridge the speed gap between processors and main memory, and are essential for improving the performance of computer systems. However, the fundamental difference in cache hit versus miss timing can be exploited to leak secret information, such as the cryptographic keys of AES and RSA ciphers. Almost all computers are vulnerable to these software side-channel attacks. Software solutions are algorithm-specific, do not apply to legacy programs and severely degrade performance. A generic hardware solution that applies to all software, does not degrade performance, and prevents all access-based cache side-channel attacks, is desirable. New security-aware cache architectures, presented in ISCA2007 , were the Random Permutation cache (RPcache) and the Partition Locked cache (PLcache). A novel cache architecture (Micro2008) is presented that not only improves security, but also improves performance, achieving the best cache access time, miss-rate and power consumption of existing classes of cache architectures. Fault-tolerance, hot-spot mitigation and flexible partitioning are additional benefits.
This talk is part of the Computer Laboratory Security Seminar series.
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Other listsThe Future of Economics and Public Policy Neuroscience CCCRR Vascular Biology Research Seminars
Other talks(In)security in a Global Age Inside Snowden’s suitcase Health Economics @ Cambridge seminar The 2015 Tissue Engineering Congress Transport Scotland TBA