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Programmable data plane

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It is challenging to provide high performance for data center services. With the ending of Moore’s law, it is no longer possible to get performance improvement by simply optimizing software. Instead, we start to rely on specialized hardware such as programmable switches, which can provide high throughput and low latency for packet processing. However, there are two challenges of using programmable switches. The first is that these switches have limited programming interfaces. We will use network telemetry as an example to show how to unlease the potential of programmable switches with approximate algorithms. The second challenge is that there are diverse programmable ASI Cs from different vendors. It is hard to program and compose diverse network-wide functions on with low-level chip-specific languages. We introduce a new language and compiler Lyra, which offers a one-big-pipeline abstraction that allows programmers to use simple statements to express their intent, while automatically compiling this big pipeline program into multiple pieces of runnable chip-specific code at switches.

Bio: Minlan Yu is a Gordon McKay professor at Harvard School of Engineering and Applied Science. She received her B.A. in computer science and mathematics from Peking University and her M.A. and PhD in computer science from Princeton University. She has actively collaborated with companies such as Google, AT&T, Microsoft, Facebook, Intel, and Bell Labs. Her research interests include data networking, distributed systems, enterprise and data center networks, and software-defined networking. She received the ACM SIGCOMM doctoral dissertation award and NSF CAREER award. She served as PC co-chair for NSDI , HotNets, and several other conferences and workshops.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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