Motivating Future Interconnects: A Differential Measurement Analysis of PCI Latency

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• David Miller (University of Cambridge)
• Thursday 08 October 2009, 16:00-17:00
• SS03, Computer Laboratory, William Gates Builiding.

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Local interconnect architectures are at a cusp in which advances in throughput have come at the expense of power and latency. Moreover, physical limits imposed on dissipation and packaging mean that further advances will require a new approach to interconnect design. Although latency in networks has been the focus of the High-Performance Computing architect and of concern across the computer community, we illustrate how an evolution in the common PCI interconnect architecture has worsened latency by a factor of between 3 and 25 over earlier incarnations.

This talk is part of the Computer Laboratory Systems Research Group Seminar series.

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