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SUMMARY:Motivating Future Interconnects: A Differential Measurement Analys
 is of PCI Latency - David Miller (University of Cambridge)
DTSTART:20091008T150000Z
DTEND:20091008T160000Z
UID:TALK19791@talks.cam.ac.uk
CONTACT:Eiko Yoneki
DESCRIPTION:Local interconnect architectures are at a cusp in which advanc
 es in throughput have come at the expense of power and latency.  Moreover\
 , physical limits imposed on dissipation and packaging mean that further a
 dvances will require a new approach to interconnect design.  Although late
 ncy in networks has been the focus of the High-Performance Computing archi
 tect and of concern across the computer community\, we illustrate how an e
 volution in the common PCI interconnect architecture has worsened latency 
 by a factor of between 3 and 25 over earlier incarnations.
LOCATION:SS03\, Computer Laboratory\, William Gates Builiding
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