HDL Code Generation from MATLAB and Simulink

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• Jon Fielder and Scott Wilson, MathWorks
• Wednesday 21 March 2012, 11:00-12:00
• SS03, Computer Laboratory.

If you have a question about this talk, please contact Prof Simon Moore.

Note unusual location

An introduction to Model-Based Design with MATLAB and Simulink focusing on HDL code generation with examples showing:

• Algorithm design in MATLAB , Simulink and Stateflow
• Generation of bit-true and cycle-accurate synthesiable Verilog and VHDL
• Control of the HDL architecture and implementation, including sharing and pipelining for trading off speed and area.
• Highlighting of critical paths in the model
• Generation of hardware resource utilization estimates
• Test bench and cosimulation approaches for rapid verification

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

This talk is included in these lists:

• All Talks (aka the CURE list)
• Cambridge talks
• Computer Laboratory Computer Architecture Group Meeting
• Department of Computer Science and Technology talks and seminars
• Interested Talks
• SS03, Computer Laboratory
• School of Technology
• Trust & Technology Initiative - interesting events
• bld31

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