University of Cambridge > > Logic and Semantics Seminar (Computer Laboratory) > Decoding Nets: A Formal Take on Address Translation

Decoding Nets: A Formal Take on Address Translation

Add to your list(s) Download to your calendar using vCal

  • UserBen Fiedler, ETH
  • ClockThursday 28 July 2022, 16:00-17:00
  • HouseFW26.

If you have a question about this talk, please contact Jamie Vicary.

Modern computing hardware is enormously complicated: a single memory request traverses multiple hardware translation and caching steps until it reaches its intended destination, which often appears at different physical addresses for different requesters.

Correctly capturing the complexity of this process is essential for correct system operation and system verification. We introduce decoding nets, a formal description for memory and interrupt systems, which we have successfully used in practice for page table generation, memory management and interrupt controller configuration.

Furthermore, we are actively using them to verify isolation guarantees of the ARM confidential compute architecture.

This talk is part of the Logic and Semantics Seminar (Computer Laboratory) series.

Tell a friend about this talk:

This talk is included in these lists:

Note that ex-directory lists are not shown.


© 2006-2024, University of Cambridge. Contact Us | Help and Documentation | Privacy and Publicity