Directed Speculation in Multi-core Memory Systems to Improve Performance and Efficiency

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• Dr. Paul V. Gratz
• Tuesday 24 April 2018, 14:00-15:00
• SS03, Computer Laboratory, William Gates Building.

If you have a question about this talk, please contact Prof Simon Moore.

The scaling of multi-core processors poses a challenge to memory system design. While process technology scaling provides greater numbers of cores on each chip, the transistor performance and power gains that traditionally accompanied process scaling have largely ceased. Scaling performance with increased core counts must be achieved under the same or reduced energy and power budgets. Furthermore, increased cores generate more accesses to shared caches causing conflict misses as unrelated processes compete for the same cache sets. Each miss represents significant waste: wasted time as the requested data is transferred from a slow main memory, wasted energy and bandwidth when transferring cache block words that will ultimately go unused. In this talk I will explore the means to leverage memory locality speculation to reduce waste and improve efficiency in multi-core processor memory systems. In particular, I will show how control flow and effective address speculation can be used in a novel prefetch engine that improves IPC by 39%, outperforming the best competing design with only 1/3 the hardware state overhead. I will also demonstrate a technique to extend this approach to speculate beyond memory synchronization semantics in multi-threaded workloads.

BIO :

Paul V. Gratz is an Associate Professor in the department of Electrical and Computer Engineering at Texas A&M University, currently visiting the University of Edinburgh on sabbatical. His research interests include efficient and reliable design in the context of high performance computer architecture, processor memory systems and on-chip interconnection networks. He received his B.S. and M.S. degrees in Electrical Engineering from The University of Florida in 1994 and 1997 respectively. From 1997 to 2002 he was a design engineer with Intel Corporation. He received his Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2008. His papers “Path Confidence based Lookahead Prefetching” and “B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors” were nominated for best papers at MICRO ‘16 and MICRO ‘14 respectively. At ASPLOS ‘09, Dr. Gratz received a best paper award for “An Evaluation of the TRIPS Computer System.” In 2016 he received the “Distinguished Achievement Award in Teaching – College Level” from the Texas A&M Association of Former Students and in 2017 he received the “Excellence Award in Teaching, 2017” from the Texas A&M College of Engineering.

This talk is part of the Computer Laboratory Computer Architecture Group Meeting series.

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