Authenticated Encryption, The CAESAR Project, and a SoC Crypto Peripheral

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• Dr. Markku-Juhani O. Saarinen ERCIM Research Fellow Norwegian University of Science and Technology, Trondheim
• Friday 08 August 2014, 16:00-16:45
• Computer Laboratory, William Gates Building, Room FW11.

If you have a question about this talk, please contact Robert Watson.

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During 2014 I’ve been involved with the U.S. NIST -funded CAESAR project (Competition for Authenticated Encryption: Security, Applicability, and Robustness). This project seeks to find secure alternatives to the Advanced Encryption Standard (AES) and more specifically its GCM Authenticated Encryption mode, which is currently the only option in NSA ’s unclassified COTS “Suite B”, certified up to Top Secret. I’ve broken a couple of CAESAR proposals and B. Minaud of French ANSSI broke my other, lightweight proposal; I will give an overview of current status of this project.

My remaining CAESAR first round candidate STRIBOB / WHIRLBOB is based on the Russian 2012 GOST hash standard “Streebog” and the ISO hash standard Whirlpool. I show how to modify the fundamental cryptographic transformation of these hashes into a Sponge-based Authenticated Encryption algorithm while maintaining a provable security link to the original well-studied algorithms. I’ll describe how a Whirlpool / AES - like MDS structure was uncovered from the GOST standard specification. I’ve met with the Russian designers of Streebog and the upcoming Russian Encryption Standard “Kuznyechik” in Moscow in June 2014. I will present some general observations on their cryptographic design strategies and recent Russian crypto policies in general.

I’ve also been building a WHIRLBOB implementation as an on-chip peripheral that sits on the AXI bus of ARM based SoCs. Such a target makes sense as it is absolutely dominant in mobile phones, tablets, and IoT devices. These are not only the most common computing and communication devices in 2014, but also most in need of power and performance optimization. I will demonstrate an implementation based on Xilinx Zynq platform, which is dual-core Cortex A9 SoC with Artix 7 FPGA Logic Fabric for peripherals (on the same chip).

This talk is part of the Computer Laboratory Security Group meeting presentations series.

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