TIADC Mismatch Compensation

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• Prof Lim Yong Ching (Nanyang Technological University, Singapore)
• Thursday 14 May 2009, 11:00-12:00
• Room 611, EEE.

If you have a question about this talk, please contact Dr George A Constantinides.

In many signal processing applications, the highest sampling speed is limited by the speed of the ADC (analog-to-digital converter). In order to achieve an AD (analog-to-digital) conversion time much shorter than can be achieved with a single ADC , a bank of properly sequenced sub-ADCs is used. Each sub-ADC samples and converts at a time displaced from the others at a regular interval. Such an AD conversion system is called a TIADC (time-interleaved ADC ). The advantages of TIADC are well known but TIADC exhibits mismatch problems that seriously degrade its performance. Conventional technique for compensating the mismatches uses a filter bank. In this talk, we present a new technique for mismatch compensation based on the generalized sampling theorem. Our new technique is computationally significantly more efficient and robust than the filter bank approach. The results of a 14-bit 1.6 GS/s (4×400 MS/s) TIADC synthesized using our new technique will also be presented.

Biography: Y. C. Lim received the A.C.G.I. and B.Sc. degrees in 1977 and the D.I.C. and Ph.D. degrees in 1980, all in electrical engineering, from Imperial College, London, U.K. From 1980 to 1982, he was with the Naval Postgraduate School, California. From 1982 to 2003, he was with the Department of Electrical Engineering, National University of Singapore. Since 2003, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University. His research interests include digital signal processing and VLSI circuits and systems design. Dr. Lim was a recipient of the 1996 IEEE Circuits and Systems Society’s Guillemin-Cauer Best Paper Award, the 1990 IREE (Australia) Norman Hayes Memorial Best Paper Award, 1977 IEE (UK) Prize and the 1974-77 Siemens Memorial (Imperial College) Award. Prof. Lim is a Fellow of IEEE . He served as a lecturer for the IEEE Circuits and Systems Society under the distinguished lecturer program from 2001 to 2002 and as an associate editor for the IEEE Transactions on Circuits and Systems from 1991 to 1993 and from 1999 to 2001. He has also served as an associate editor for Circuits, Systems and Signal Processing from 1993 to 2000. He served as the Chairman of the DSP Technical Committee of the IEEE Circuits and Systems Society from 1998 to 2000. He served in the Technical Program Committee’s DSP Track as the Chairman in IEEE ISCAS ’97 and IEEE ISCAS ’00 and as a Co-chairman in IEEE ISCAS ’99. He is the General Chairman for IEEE APCCAS 2006 and a Co-General Chairman for IEEE ISCAS 2009 .

This talk is part of the CAS FPGA Talks series.

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• CAS FPGA Talks
• Room 611, EEE

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