Latency in PCI

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• David Miller (University of Cambridge)
• Tuesday 17 February 2009, 13:00-13:30
• Computer Laboratory, William Gates Building, Room FW11.

If you have a question about this talk, please contact Stephen Kell.

In search of ever greater performance, PCI bus evolved from a simple 32 bit parallel 33 MHz bus to today’s incarnation, multilane, multigigabit serial. While bandwidth has gone up, so apparently has latency. I present the results of a set of experiments which investigate the relative performance of different kinds of PCI bus, and speculate as to the consequences of these results.

This talk is part of the Computer Laboratory NetOS Group Talklets series.

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