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SUMMARY:Latency in PCI - David Miller (University of Cambridge)
DTSTART:20090217T130000Z
DTEND:20090217T133000Z
UID:TALK17097@talks.cam.ac.uk
CONTACT:Stephen Kell
DESCRIPTION:In search of ever greater performance\, PCI bus evolved from a
  simple 32 bit parallel 33 MHz bus to today's  incarnation\, multilane\, m
 ultigigabit serial. While bandwidth has gone up\, so apparently has latenc
 y.  I present the results of a set of experiments which investigate the re
 lative performance of different kinds of PCI bus\, and speculate as to the
  consequences of\nthese results.\n
LOCATION:Computer Laboratory\, William Gates Building\, Room FW11
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