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SUMMARY:(FPT Preview) A Transition Probability Based Delay Measurement Met
 hod for Arbitrary Circuits on FPGAs - Justin Wong (Imperial College London
 )
DTSTART:20081128T150000Z
DTEND:20081128T153000Z
UID:TALK15444@talks.cam.ac.uk
CONTACT:Dr George A Constantinides
DESCRIPTION:This paper proposes a novel test method for measuring the wors
 t case path delay of any circuit on an FPGA\, combinatorial or sequential\
 , where little prior knowledge of the circuit’s internal structure is re
 quired. The method is based on detecting changes in the transition probabi
 lity profile on the circuit’s output nodes while a range of test clock f
 requencies is stepped through. The method is applied to three classes of c
 ircuits\, all implemented on an Altera Cyclone III FPGA: an adder carry ch
 ain\, an embedded multiplier and a linearfeedback shift-register. The meas
 ured delays are compared to that found by a previously published\, but muc
 h more time consuming\, method and their results match to within 12%.
LOCATION:Mahanakorn Laboratory\, EEE
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