University of Cambridge > Talks.cam > CAS FPGA Talks > (FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining

(FPT Preview) Co-optimisation of Datapath and Memory in Outer Loop Pipelining

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When targeting algorithms to FPGA based systems both the array to memory assignment and the selection of data reuse structures must often be considered to maximise performance. In this work we present an Integer Linear Programming formulation for the combined problem of array to memory assignment and data reuse selection. We include a number of cost functions to minimise during memory optimisation and show how these optimisations can be integrated into a loop pipelining framework to iteratively update the memory subsystem during scheduling. By co-optimising the datapath (schedule) and memory subsystem we are able to produce near optimal (fastest) solutions, with an upper bound on the distance from the optimal solution. Our results show an average speedup of up to 4x over a non-optimised memory subsystem when integrated into an existing outer loop pipelining framework.

This talk is part of the CAS FPGA Talks series.

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