'A linear algebra framework for automatic determination of optimal data layouts' by Mahmut Kandemir et al.

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• Sam Bayliss (Imperial College London)
• Wednesday 17 December 2008, 12:00-12:30
• 503, EEE.

If you have a question about this talk, please contact Dr George A Constantinides.

In this talk – I’ll make a brief presentation of a 1999 “IEEE transactions on Parallel and distributed systems” paper by Mahmut Kandemir in which he presents a formal definition of spatial and temporal locality in terms of hyperplanes and determines optimal memory layouts for arrays accessed within loop nests.

The principles explained will probably seem obvious to those who’ve been doing memory oriented work and easily accessible to those in the group who have been working in other areas.

This talk is part of the CAS FPGA Talks series.

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• 503, EEE
• CAS FPGA Talks

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