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SUMMARY:RISC Instructions for Capability Acceleration - Jonathan Woodruff
DTSTART:20110610T150000Z
DTEND:20110610T160000Z
UID:TALK31763@talks.cam.ac.uk
CONTACT:Robert Mullins
DESCRIPTION:The CTSRD project at the Cambridge Computer Laboratory is deve
 loping a MIPS processor with custom security extensions to accelerate capa
 bility systems.  Capability hardware systems allow the enforcement of the 
 principle of least privilege in the lowest levels of computation.  In the 
 1960s and 70s there was much exploration in this space but the market did 
 not demand such stringent security.  Security issues are now much more thr
 eatening in the market and we are building an extended MIPS processor to e
 nable fast capability-based systems which is also able to run legacy softw
 are natively.  I will describe the processor architecture designed so far 
 and software use models planned by our systems team.
LOCATION:SC04\, Computer Laboratory\, William Gates Building
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