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SUMMARY:Link-Time Optimization for Instruction Cache Power Efficiency - Ti
 mothy Jones
DTSTART:20110513T150000Z
DTEND:20110513T160000Z
UID:TALK31301@talks.cam.ac.uk
CONTACT:Robert Mullins
DESCRIPTION:The instruction cache is a critical component in any microproc
 essor which must have high performance to enable fetching of instructions 
 on every cycle.  However\, current designs waste a large amount of energy 
 on each access as tags and data banks from all cache ways are consulted in
  parallel to fetch the correct instructions as quickly as possible. Existi
 ng approaches to reduce this overhead remove unnecessary accesses to the d
 ata banks or to the ways that are not likely to hit.  However\, tag banks 
 still need to be checked\, which wastes power if you know exactly where th
 e required instructions are in the cache.\n\nThis talk presents a new hybr
 id hardware and linker-assisted approach to tagless instruction caching.  
 Our novel cache architecture\, supported by the compilation toolchain\, re
 moves the need for tag checks entirely for the majority of cache accesses.
   The linker places frequently-executed instructions in specific program r
 egions that are then mapped into the cache without the need for tag checks
 .  This requires minor hardware modifications\, no ISA changes and works a
 cross cache configurations. Our approach keeps the software and hardware i
 ndependent\, resulting in both backward and forward compatibility.\n\nEval
 uation on a superscalar processor with and without SMT support shows power
  savings of 66% within the instruction cache with no loss of performance. 
  This translates to a 49% saving when considering the combined power of th
 e instruction cache and translation lookaside buffer\, which is involved i
 n managing our tagless scheme.\n
LOCATION:SC04\, Computer Laboratory\, William Gates Building
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