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SUMMARY:Performance Comparisons of Hard Logic\, Programmable Soft Logic\, 
 and Instruction Set Architectures - Jonathan Rose - University of Toronto
DTSTART:20091209T141500Z
DTEND:20091209T151500Z
UID:TALK21724@talks.cam.ac.uk
CONTACT:Mateja Jamnik
DESCRIPTION:The excitement and creativity in the field of computing has be
 en enabled by the exponential progress of the underlying circuit fabricati
 on technology.  Despite this\, it is rare that researchers (or industry) c
 reate their own chips because it is simply too difficult and expensive\, b
 ut rather use programmable pre-fabricated instruction set processors.\n\nT
 he other widely-used way of leveraging the underlying chip fabrication tec
 hnology is to employ Field-Programmable Gate Arrays (FPGAs) which are made
  of fine-grained units of logic and memory that can be programmably interc
 onnected at the electrical level\, bit-wise.\n\nFPGAs and instruction set 
 processors are capable of implementing similar things\, but each has diffe
 rent strengths as measured by cost\, speed\, energy consumption and ease o
 f use.  In this talk\, I will present an overview of several research proj
 ects that compare FPGA cost\, performance and power consumption against ot
 her implementation 'media':\n\n    # Hard\, fully-fabricated integrated ch
 ips (often referred to as ASICs).\n    # High-performance uniprocessors.\n
     # General Purpose Graphics Processing Units (GP GPUs).\n    # Soft Pro
 cessors and Soft Vector Processors \n       (processors built on top of FP
 GA fabrics)\n\nAlthough these were independent comparisons (each driven by
  different applications)\, I will also try to glue them together and see h
 ow the results reflect the strengths and weaknesses of each computation me
 dium\, and discuss the implications for future directions in programmable 
 architectures.\n
LOCATION:Lecture Theatre 1\, Computer Laboratory
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