BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//talks.cam.ac.uk//v3//EN
BEGIN:VTIMEZONE
TZID:Europe/London
BEGIN:DAYLIGHT
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
TZNAME:BST
DTSTART:19700329T010000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
TZNAME:GMT
DTSTART:19701025T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
CATEGORIES:Computer Laboratory Computer Architecture Group Me
 eting
SUMMARY:Design\, Compilation and Runtime Solutions for Ene
 rgy-Efficient Microprocessors - Timothy Jones\, Un
 iversity of Edinburgh
DTSTART;TZID=Europe/London:20081013T140000
DTEND;TZID=Europe/London:20081013T150000
UID:TALK14459AThttp://talks.cam.ac.uk
URL:http://talks.cam.ac.uk/talk/index/14459
DESCRIPTION:For the last 30 years\, Moore's law has delivered 
 an exponential growth in the number of transistors
  on an integrated circuit\, enabling higher clock 
 frequencies and better processor performance. Howe
 ver\, as transistor sizes have shrunk\, the amount
  of energy consumed by each processor has been inc
 reasing steadily. Power is now a first-class desig
 n constraint\, requiring sophisticated packaging a
 nd cooling systems to be provided that can remove 
 the generated heat from the processor. This talk w
 ill examine recently-proposed schemes to tackle th
 is energy problem at three different stages in a s
 ystem's life cycle: at design\, compilation and ru
 ntime. It will consider the use of machine learnin
 g to design energy-efficient architectures and pre
 dict the performance that an optimising compiler c
 an achieve on them. It will also examine a hybrid 
 compilation / runtime scheme that saves energy in 
 the instruction cache through a profile-directed c
 ode placement strategy.
LOCATION:Lecture Theatre 2\, Computer Laboratory\, William 
 Gates Building
CONTACT:Robert Mullins
END:VEVENT
END:VCALENDAR
