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DTSTART:19700329T010000
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CATEGORIES:CAS FPGA Talks
SUMMARY:Low-Power Design for Reconfigurable Computing - Dr
  George A Constantinides (Imperial College London)
DTSTART;TZID=Europe/London:20080715T113000
DTEND;TZID=Europe/London:20080715T123000
UID:TALK12748AThttp://talks.cam.ac.uk
URL:http://talks.cam.ac.uk/talk/index/12748
DESCRIPTION:In this talk\, we will focus on the sources of pow
 er consumption in modern reconfigurable logic devi
 ces (FPGAs) implementing numerical algorithms. The
  requirement for early-stage power estimation mode
 ls for arithmetic circuits will be developed\, and
  the challenges involved will be discussed. Some r
 esults from our research indicating the accuracy a
 chievable at various levels of abstraction will be
  presented. We will close with one suggested use f
 or high-level power models: allowing the automatic
  optimal tradeoff of power consumption for arithme
 tic roundoff error.
LOCATION:Mahanakorn Laboratory\, EEE
CONTACT:Dr George A Constantinides
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